Got stuck during establishing ethernet Communicaton using Quartus prime and Nios software.

Hi,

I have an update regarding the loopback test:

Code Overview

In the Main_Code file, I implemented the loopback test as follows:

=====================================================================

void ethernet_loopback_test() {
// Initialize TSE and PHY
InitNetwork(); // Initialize the Triple-Speed Ethernet (TSE) IP
printf("TSE initialized.\n");
printf("PHY internal loopback mode configured.\n");

// Prepare Ethernet packet (64 bytes)
uint8_t tx_packet[64] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // Destination MAC (broadcast)
0x00, 0x07, 0xAB, 0xF0, 0x0D, 0xBA, // Source MAC (example)
0x08, 0x00, // Ethertype (IPv4)
0x45, 0x00, 0x00, 0x2E, // IPv4 header (first bytes, rest as padding)
0x00, 0x00, 0x40, 0x00, 0x40, 0x11, // More IPv4 header
0xB8, 0x61, // Checksum (placeholder)
0xC0, 0xA8, 0x00, 0x19, // Source IP (192.168.0.25)
0xC0, 0xA8, 0x00, 0x1A, // Destination IP (192.168.0.26)
// Rest of the payload (padding for simplicity)
0xDE, 0xAD, 0xBE, 0xEF, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};

// Transmit packet
tse_mac_sTxWrite(tx_packet, sizeof(tx_packet));
printf("Packet transmitted.\n");

// Receive looped-back packet
uint8_t rx_packet[64] = {0}; // Initialize the receive buffer with zeros
tse_mac_aRxRead(rx_packet, sizeof(rx_packet));
printf("Packet received.\n");

// Compare transmitted and received packets
if (memcmp(tx_packet, rx_packet, sizeof(tx_packet)) == 0) {
printf("Loopback test successful! Packets match.\n");
} else {
printf("Loopback test failed. Packets do not match.\n");
}
}

=============================================================

Additionally, in the Altera_Avalon_tse.h file, I enabled the PHY loopback for debugging purposes by setting:

#ifndef ENABLE_PHY_LOOPBACK
#define ENABLE_PHY_LOOPBACK 1
#endif

Observations

After making these changes, the Nios II console output displays "Putting PHY in Loopback," followed by the warnings "WARNING: TX SGDMA Timeout."

I've attached a screenshot ("Nios II - Debug - Screenshot -1") for reference.

Further Analysis

I noticed that the Tx enable signal and the Tx data signal remain at "0" (both in and out of loopback mode). During debugging, I found that the Tx_clock from the PHY IC is fixed at 2.5 MHz, regardless of the speed configured in the Nios II software.

Interestingly, the Rx_clock changes correctly when I adjust the Ethernet speed settings on the PC (2.5 MHz, 25 MHz, 125 MHz, etc.). The data is also successfully captured in Signal Tap during a ping operation, indicating no issues on the receiving side or with the hardware design.

The problem seems to be on the transmitting side, where we are unable to configure the PHY IC correctly.

I would greatly appreciate your assistance in troubleshooting this Tx_clock issue. Please help me resolve this problem. I've also attached the project folder link for your reference.

Thank you for your support!