Got stuck during establishing ethernet Communicaton using Quartus prime and Nios software.

Hello,

I downloaded the example projects you shared and began working on them. Since we are using a custom-designed board with a Cyclone V FPGA (5CEFA7F27I7), a DP83867IR, and an SDRAM IC, I modified the necessary IPs and removed the unnecessary ones in the QSYS. After compiling and running the program, I encountered Makefile and .elf errors while building in the Nios II software, but the exact errors were not displayed.

Observations from My Previous Project:

• There were no errors in the Nios II console output, but the ping between the PC and the board still could not be established.
• The board is receiving data but failing in transmission. When checked with the Signal Tap logic analyzer, I found that the pinging data transmitted from the PC is received through the FPGA's input pin via the PHY IC. However, the FPGA is neither transmitting data nor enabling the transmit enable signal.
• It appears that the PHY IC is not being programmed correctly, resulting in a clock rate mismatch. The Tx_clk frequency from the PHY IC is 2.5 MHz instead of the expected 25 MHz (screenshots are attached).

I would appreciate it if you could provide some guidelines on performing a loopback test. Additionally, it would be helpful if you could share any C programming code examples for executing a loopback operation.

Thank you for your time and assistance.

Best regards,
Prajwal RJ