New Contributor
New ContributorI also have the same question. The Generic Serial Flash Interface Intel FPGA IP simply shows a 4-bit QSPI data line. There is no instruction in the user guide (https://www.intel.com/content/www/us/en/docs/programmable/683419/24-1-20-2-5/user-guide.html) for how to set up single mode! Are we supposed to guess and check where the MOSI & MISO lines go?
Come on Intel/Altera! 5 years since the original post and still no answer?? Disappointing.
Super ContributorHi,
the answer is in any QSPI flash datasheet of your choice. Flash SPI access always starts in single mode, therefore they have a fixed mapping of MOSI (flash DI) and MISO (flash DI) to IO[3:0] lines. You'd know if you read any. DI is IO0, DO IO1. The assignment should be fixed in a JEDEC standard, I didn't check because it's obvious for me.
Anyway I agree that the question could have been answered clearly from the start.
