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dsun01's avatar
dsun01
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3 years ago
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fundamental question about Jesd204b II

Dear Intel Support/Expert, I created a Jesd204b IP with the following parameters. in main page, Device Family: Arria10, "both base and phy", "Receiver", subclass "1", Data rate" 6144Mbps. "enab...
  • skbeh's avatar
    skbeh
    3 years ago

    Hi Havid

    The timing reference clock for the JESD204B IP core (txlink_clk, rxlink_clk) runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/10B encoding.

    So far I have not seen the use case of data rate/80.


skbeh's avatar
skbeh
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3 years ago

Hi Havid

The timing reference clock for the JESD204B IP core (txlink_clk, rxlink_clk) runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/10B encoding.

So far I have not seen the use case of data rate/80.


  • dsun01's avatar
    dsun01
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    3 years ago

    thank you very much.