Frame Reader Initialization

I put the frequency of the onchip memory to 27 MHz and changed my interrupt service routine to the recomendations considering to clear the enable bit before sending out the next frame (thank you kevin). Now the frame reader can read data from the onchip memory and stream valid avalon video and data packets to the alpha blending mixer.

Altera has following workaround for the issue with the interrupt which is not connected, which I have tested successfully with the frame reader design reading data from onchip memory:

to fix the interrupt connectivity issue, you have to change the file "c:\altera\91

\ip\altera\frame_reader\src_hdl\alt_vipvfr91_vfr.v" on line 279

From:
.interrupts (interrupts),
To:
.interrupts (irq_FROM_controller_TO_slave),

In Quartus II service pack 2 the issue will be solved.

I have also a design in which the onchip memory is replaced by a DDR SDRAM and instead of reading from the onchip memory it reads its data from the DDR SDRAM. However, there seem to be bandwith problems yet, since I can show a valid picture, with a limited width only.