Frame Reader Initialization

My experience with the end of frame interrupt is that it does not work.

If you search for the irq signal in the post mapping net list viewer you will see it get's optimized out and that there is no interrupt connection between the frame reader and Nios. The source code for the frame reader is actually included with Quartus. I did manage to patch it to make the interrupt work. I sent all the details to my Altera FAE, but I never heard anything back about it.

In the end, I was able to write my own frame reader from scratch in less time than it took me to get the VIP frame reader doing what I wanted. My version also used a fraction of the logic elements. My version is also less capable in some ways, but it did everything I needed.

To answer your other questions:

Bit 1 is the second bit, bit 0 is the first.

You need to manually reset the interrupt in your ISR. For example: IOWR(BASE, 2, 2);