For Cyclone 10 is it acceptable to generate CLKUSR from a PLL?

Question

We are using the Cyclone 10 PCIe Hard IP.  Is it acceptable to generate the CLKUSR clock from a PLL in the same device?  We are not concerned about the delay that will be caused.

rahul_s_intel1 · Answer

better to use from the FPLL

rahul_s_intel1 · Answer

I am also assuming you are using Cylcone 10 GX

Forum Discussion

For Cyclone 10 is it acceptable to generate CLKUSR from a PLL?

2 Replies

Recent Discussions

Can't generate F-Tile Ethernet Hard IP Design Example

MAX10 TSE reference design

Accessing registers in the PCIE IP beyond MCDMA using system console

Constraints not being picked for DCFIFO

Cyclone IV GX project failed migration from 20.1 to 23.1std