Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThanks a lot for the new design.
--- Quote Start --- I'm not sure I follow what you're saying. --- Quote End --- What Im trying to say is that if the Latency parameter was : 'the number of cycles you would wait to see the output asserted after asserting the input', if we take into account the 'Zero latency example', lets say a t=0 we change the input, at the output we will have: at t=0 the valid signal at only at t=10 the asserted output. Should not it be better in that case let the DSP builder set the Latency parameter at 10 instead of 0 ?