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And if it was like in this case that we supply the data just once? I have attached my design, the only way that I can think to have something like that is to put a FF just before d0 driven by the valid signal, but how to do this in DSP?
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I've attached how the demo_fibonacci design should be modified using to use floating point. One modification I made was to the test bench. I changed it so that valid is held high for enough cycles to clear the Sample Delays, i.e. at least 28 cycles. The design is really misusing valid. It's really just an input that signals that the data should be reset in this case.
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In the first place this was what I got, but then I changed idea reading the attached 'Zero Latency Example' of the 'DSP Builder Handbook Volume 3'.
I mean your statement is true only if we set latency constrains in cases like the Zero Latency; am I right?
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I'm not sure I follow what you're saying.
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