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One way to do this would be to supply data at a slower rate than the clock rate. E.g. Have valid go high only once every twelve cycles, then increase the Sample Delay lengths in your design to 12.
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And if it was like in this case that we supply the data just once? I have attached my design, the only way that I can think to have something like that is to put a FF just before d0 driven by the valid signal, but how to do this in DSP?
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Assuming you wired the valid input directly up to the valid output, then the latency parameter should give you the number of cycles you would wait to see the output asserted after asserting the input.
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In the first place this was what I got, but then I changed idea reading the attached 'Zero Latency Example' of the 'DSP Builder Handbook Volume 3'.
I mean your statement is true only if we set latency constrains in cases like the Zero Latency; am I right?
Thanks in advance
Honored Contributor
