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I have just implemented the Fibonacci design explained on the ch4 Primitive Library Tutorial.
I wanted to try it using floating point numbers so i changed the parameters of the blocks, after the first run I get the following error:
Failed to distribute memory in your design.
Found insufficient delay around the following registers while attempting to satisfy fMax requirement for [Subsystem]. Increase latency around this loop by at least 12, or reduce the fMax requirement. (Note that there may also be other failing loops).
Then I added the extra delays in the loop (the fMax was only 1 MHz) and I got the output showed in the attached file, which makes sense after having analyzed the system.
My questions are:
1- Do I need extra delays with the floating number because of the complex design to manage them?
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The reason you need more delay than if it was implemented in fixed point is that a floating point add has more pipelining stages. Floating point pipelining in DSP Builder is not quite as advanced as fixed point pipelining so reducing the FMax won't help in this situation.
Any designs with feedback loops will have this problem as they can do with fixed point designs.
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2- How in this case should I change the design to work properly?
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One way to do this would be to supply data at a slower rate than the clock rate. E.g. Have valid go high only once every twelve cycles, then increase the Sample Delay lengths in your design to 12.
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3- I didnt fully get the sense of the Latency param on the channel out, does it simply show the number of the pipeline stage added to get the maximum efficiency? If yes which is the useful thing about that? Could it not be more useful showing just the Latency of the entire subsystem?
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Assuming you wired the valid input directly up to the valid output, then the latency parameter should give you the number of cycles you would wait to see the output asserted after asserting the input. It's a bit more complicated than just the number of pipeline stages added because of the effect of sample delays.
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