Forum Discussion
Altera_Forum
Honored Contributor
14 years agoAt a guess that is an 'optimisation' (or maybe a bug) in the VHDL to avoid the extra comparator and shifter/mux required to process the subnormal value.
Support for subnormal values as well as INF, NaN, -0 and the rounding rule(s) could be logic saving options for any FP unit.