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That is the latency of registers. Without registers(and this is not realistic) you will have zero latency.
Probably you are thinking of group delay, this is signal delay through filter and is equal to (taps-1)/2 and means if you input a sine wave then its peak will be delayed that much.
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Yes. I am talking about filter inputs to filter output delay. I am using 50 taps. and I can see in my waveforms the first input sample delayed by 50 samples. At the same time the first valid output asserted 6 samples after the first valid input is asserted. Please see the attached waveforms.
Does it mean the first 44 samples I see in my simulation waveforms are garbage?
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