fir_compiler+ii error id 15008

I have created a decimation filter using MegaCore FIR Compiler II, this produces the frequency plot I want and compiles without errors.

When I add this to my design in Quartus and compile I get the following error messages:-

15008 MLAB "dsp_block:inst 27| ................. |altsyncram_atv3:auto_generated|lutrama0" on port "Port A, data In" has illegal width "0". The correct width is "1"

15010 MLAB "dsp_block:inst 27| ................. |altsyncram_atv3:auto_generated|lutrama0" is implementing memory in non-ROM mode, but the port "Port A, Data In" is not connected

15464 WYSIWYG primitive "dsp_block:inst 27| ................. |altsyncram_atv3:auto_generated|lutrama0" has mismatched parameters for port Port A, Data In

Any help on how to fix this would be much appreciated

Using Quartus V14.0

Device Cyclone V 5CSEBA6U23I7

filter.vhd

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---->

-- Retrieval info: <instance entity-name="altera_fir_compiler_ii" version="14.0" >

-- Retrieval info: <generic name="deviceFamily" value="Cyclone V" />

-- Retrieval info: <generic name="filterType" value="Decimation" />

-- Retrieval info: <generic name="interpFactor" value="1" />

-- Retrieval info: <generic name="decimFactor" value="8" />

-- Retrieval info: <generic name="L_bandsFilter" value="All taps" />

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-- Retrieval info: <generic name="outLsbBitRem" value="15" />

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