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Altera_Forum's avatar
Altera_Forum
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16 years ago

FIR Compiler troubles

Hi,

Help is needed.

I am trying to design a system with a filter; I’m using the FIR Compiler to generate the filter component.

At this moment I’m just experimenting by choosing different filter options and looking how many logic resources it would take.

But I faced a problem that I cannot resolve by myself – When I run Quartus II compiler/fitter I get the following warnings:

Warning: Output pins are stuck at VCC or GND

Warning (13410): Pin "source_data[16]" is stuck at GND

Warning (13410): Pin "source_data[15]" is stuck at GND

…

Warning (13410): Pin "source_data[0]" is stuck at GND

Warning: Design contains 8 input pin(s) that do not drive logic

Warning (15610): No output dependent on input pin "sink_data[7]"

Warning (15610): No output dependent on input pin "sink_data[6]"

Warning (15610): No output dependent on input pin "sink_data[5]"

Warning (15610): No output dependent on input pin "sink_data[4]"

Warning (15610): No output dependent on input pin "sink_data[3]"

Warning (15610): No output dependent on input pin "sink_data[2]"

Warning (15610): No output dependent on input pin "sink_data[1]"

Warning (15610): No output dependent on input pin "sink_data[0]"

Warning: Following 17 pins have nothing, GND, or VCC driving datain port -- changes to this

connectivity may change fitting results

Info: Pin source_data[16] has GND driving its datain port

Info: Pin source_data[15] has GND driving its datain port

Info: Pin source_data[14] has GND driving its datain port

……

There warnings are very important since I see that something is implemented incorrectly in the filter.

Can you suggest me what can be reason of the problem? I did the following steps only:

  • Created Quartus project, added bdf file

  • Created a filter component using the FIR Compiler ( I did a screenshot of my filter parameters, in filter.jpg file) and added it to the bdf file.

  • 3. Added some input/ output pins, connected them using Pin Planner to the I/O pins of FPGA (cyclone II EP2C20F484C7), clock is connected to the PIN_L1. I attached a screenshot of the bdf file – its bdf.jpg

  • 4. Run compilation
On which stage I did/didn’t something wrong? I appreciate any help and suggestions.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    First two warnings are related to bit width of FIR filter coefficients due to no scaling. There's no problem with this. But, i'm not sure about input warnings, this connection isn't clear in image.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    First two warnings are related to bit width of FIR filter coefficients due to no scaling. There's no problem with this. But, i'm not sure about input warnings, this connection isn't clear in image.

    --- Quote End ---

    Thank you very much, parrado.

    What else should I check to make it clear what can cause the input warnings?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I found something new. Previously I had the "ast_source_ready" port unconnected. Now I connected it to a pin "source_ready" and the following error appeared:

    Error: Inconsistent dimensions for element "source_ready"

    Error: Can't elaborate top-level user hierarchy

    So now I cannot compile the design at all. I have no idea, completely, how to solve the problem.:(