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Altera_Forum
Honored Contributor
16 years agoFIR Compiler 9.1 generate incorrect outputs
Hi, I created a simple simulink model using DSP builder 9.1 sp1 blocks. The model runs at 120Mhz with 20.02Mhz input signal. After generating 20Mhz cos and sin signals from NCO block, the...
Altera_Forum
Honored Contributor
16 years agoIt might help if you send me text file of your output data