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Altera_Forum
Honored Contributor
16 years agoFIR Compiler 9.1 generate incorrect outputs
Hi, I created a simple simulink model using DSP builder 9.1 sp1 blocks. The model runs at 120Mhz with 20.02Mhz input signal. After generating 20Mhz cos and sin signals from NCO block, the...
Altera_Forum
Honored Contributor
16 years agoI don't have your tools but as you said, you get -0.02MHz and 40.02MHz.
I checked your filter coefficients and it works and removes 40.02MHz. You are left with -0.02MHz. Your 0.02MHz will need several thousand samples to show one period. May be you are looking at few samples.