Forum Discussion
FIFOed UART Qsys Generation Error with Qsys Standard v18.1
Hello,
when generating a FIFOed UART with Qsys Standard v18.1 as provided here
I receive the following Qsys generation errors:
Info: tube_uart_0: Starting FIFOed UART Generation at C:/xy/Qsys/fifoed_uart
…
Info: tube_uart_0: Starting RTL generation for module 'f2flink_tube_uart_0'
…
Info: tube_uart_0:
Info: tube_uart_0: ERROR:
Info: tube_uart_0: no width for __0__/* synthesis keep */
Error: tube_uart_0: Failed to generate module f2flink_tube_uart_0
Info: tube_uart_0: Done RTL generation for module 'f2flink_tube_uart_0'
Info: tube_uart_0: "f2flink" instantiated fifoed_avalon_uart "tube_uart_0"
Error: Generation stopped, 15 or more modules remaining
This issue seems to be related to the Tx FIFO option (see screenshot).
Could you please let me know how this problem can be fixed and if a patch is available? Thank you.
Best regards,
Thomas
23 Replies
- KennyT_altera
Super Contributor
You mention that you was able to reproduce the issue, are you using windows 7? As mention, I am using windows 10 and redhat. Would you able to use windows 10?
For reset password problem, can you file a new thread to address this differently?
- TMK
New Contributor
My colleague has Windows 10 installed on his machine and is able to reproduce the problem as well. Could you please try again on Windows 10?
- KennyT_altera
Super Contributor
Today I tried again and I am getting error in windows 10, seems like I might have choose the wrong language in my previous test.
Error: fifoed_avalon_uart_0: Failed to generate module Test_fifoed_avalon_uart_131_rxorl4y
Info: fifoed_avalon_uart_0: Done RTL generation for module 'Test_fifoed_avalon_uart_131_rxorl4y'
Error: Generation stopped, 1 or more modules remaining
Info: Test: Done "Test" with 3 modules, 1 files
Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings
If you swith from VHDL to verilog for simulation, the error goes away. Since modelsim able to support mixed language simulation, you will have to choose Verilog instead.
Please note that there will be no fixed/support for old version of IP (in your case Q13.1). We are sorry to inform that.
- TMK
New Contributor
You mentioned that this is an old version of IP which implies that there is a newer one that is still under support. Could you please provide the version that is under support?
- KennyT_altera
Super Contributor
Unfortunately, nope. Usually, if the IP official support from the engineering, you will not need to downloading in the website. It will be exist in the Installed IP when you install the Quartus Prime.
However, if you wish to have this IP. What I can do is file an enhancement to our engineering to include this IP in the future release of Quartus Prime Pro.
- TMK
New Contributor
So I understand that this IP never was really under support from Intel. I think that mainly customers in the low-cost field using the Quartus Prime Standard edition would benefit the most. I don't work with the Pro edition but I think that other users could benefit from it. But who knows, in a data center a UART is probably not the interface of choice.
- KennyT_altera
Super Contributor
understood, I will try to get this enhancement done on Standard as well.