New Contributor
Super ContributorToday I tried again and I am getting error in windows 10, seems like I might have choose the wrong language in my previous test.
Error: fifoed_avalon_uart_0: Failed to generate module Test_fifoed_avalon_uart_131_rxorl4y
Info: fifoed_avalon_uart_0: Done RTL generation for module 'Test_fifoed_avalon_uart_131_rxorl4y'
Error: Generation stopped, 1 or more modules remaining
Info: Test: Done "Test" with 3 modules, 1 files
Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings
If you swith from VHDL to verilog for simulation, the error goes away. Since modelsim able to support mixed language simulation, you will have to choose Verilog instead.
Please note that there will be no fixed/support for old version of IP (in your case Q13.1). We are sorry to inform that.
New ContributorYou mentioned that this is an old version of IP which implies that there is a newer one that is still under support. Could you please provide the version that is under support?
