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Altera_Forum
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14 years ago

FIFO Underflow in CVO

Hi, I am havin FIFO underflow in my design. It works fine and I see the output (DVI 1080 progressive input video and output video) on display with the nios ii processor with run time control o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The purpose of adding the clock crossing bridge was to have a buffering mechanism to pipeline multiple read and write transfers. There is an initial latency penalty for first read and write operation but it has a parameterizeable FIFO for slave to master and master to slave signals thus allowing burst transfers across clock domains. It can queue multiple transfers to maintain the system throughput.

I think I have serious bandwidth problem in the design that is what I could make out by reading other posts on the same topic. But dont know how to remove them.

Any help ??