Honored Contributor
Honored ContributorThe purpose of adding the clock crossing bridge was to have a buffering mechanism to pipeline multiple read and write transfers. There is an initial latency penalty for first read and write operation but it has a parameterizeable FIFO for slave to master and master to slave signals thus allowing burst transfers across clock domains. It can queue multiple transfers to maintain the system throughput.
I think I have serious bandwidth problem in the design that is what I could make out by reading other posts on the same topic. But dont know how to remove them. Any help ??
