Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

FIFO IP is getting empty at a faster rate

Hi, I'm using a FIFO IP with width of the fifo being 16 bit and the depth of the fifo buffer is 16384 words. I'm using the MAX10 development kit and interfacing it with Matlab. The baud rate is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

Make sure you have a proper level shifting buffer between FPGA I/O pins & the external RS-232 connector since the I/O buffers on most Altera FPGA families do not comply with RS-232 voltage levels, and may be damaged if driven directly by signals from an RS-232 connector.

Can you elaborate more on the problem? How fast it is getting emptied?

--- Quote End ---

Hi,

Thanks for this information. I didn't know that. I need to look into this too.