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Altera_Forum
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9 years ago

FIFO filling up after 2 writes

Hi, I'm using a 32 bit FIFO set to show-ahead, to cross clock domains from a fast clock to a slower clock. The FIFO is empty and i clock in two 32 bit words, i invert the rdempty signal a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Did you write your own FIFO logic?

It seems that the extra read cycle from the second read causing the FIFO counter to loop (overflow) to maximum value of 1023. If you write your own logic, you might want to detect the counter == 0 and prevent the read.