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Altera_Forum
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11 years ago

FFT problem. Simulation vs HW's execution

Hi, I'm having some problems with the utilization of the FFT IP from altera. I have a architecture that uses 4 FFTs in paralel. The simulation in the modelsim the project is doing fine. But when I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

If timing report is ok then at least we know that internal logic (fft) should behave well at any speed up to fmax.

If io constraints are not right but you are not reading them in your analysis (rather you read inputs/outputs of fft directly) then you can ignore io for now.

try freezer testing if it forces a change.