FFT problem. Simulation vs HW's execution

The plataform that the GIDEL provides look like this:

It has a memory controller that reads or writes data from/to the DDR2 and it has the interface based in FIFOs. The controller makes a burst to read some data and store it in FIFOs, so when the user makes a request of a new data, he is actually reading the FIFO. The write operation is look like, the user writes in another FIFO and the controller reads the data from that FIFO and makes a burst to the DDR2.

The clock is one input of the top module of the plataform. The clock is generated on PLL outside the top module of the plataform. It is configured by SW, so in the application that communicates with the HW you can define the frequency of the clock.

So the data that is inputed in the FFTs are not coming from the pins of the FPGA, and the data generated by then is not going to the pins, too.

I've already checked the inputs and outputs of the FFTs in the signaltaps. There, I've seen that the inputs are being provided in the same time to all 4 FFTs (same clock cycle), but the response of one FFT is one clock cycle before or after the others. And in the signaltap i've seen that the outputs values were wrong. For example, sometimes the expoent were giving a positive value, and according to the documentation it is impossible.

The inputs of each FFT is different from another, but i've compared each input and output of the FFTs in HW with the inputs and outputs of the simulation.

Thanks.