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Thank you very much for your reply! And I have an additional question regarding to the FFT IP core output data streaming. From the specs, I know that the output is a sourcing data. Does the data have to connect with Avalon ST? Can I use normal wire connection to make the data passing to the next block? And additionally, in order to get the real output of the FFT result, a shifting of original data should be performed based on exponent, right? In order to shifting the original data, more than one cycle will be needed. However, the output of the data is a streaming data bus, which keeps streaming data as long as the FFT transform is done. Is there a way to control the fft ip core output? If not, how to achieve controlling the data streaming in order to perform the shifting bits without messing with the timing constraint? Thank you very much! I am looking forward to your reply!
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you can connect fft output to any block provided you pass source vld.
You don't need clock cycles and you don't need shift, just put zeros in LSBs or remove LSBs as required in one go.
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