Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

FFT Megacore

Hi everyone!

I'm currently working on a university project, based on the implementation of FFT on a FPGA. I read about the possibility to use the FFT Megacore. Can i found this IP in Quartus II Web Edition ? How does it work ? it is similar to a core belonging to a library that must be declared at the beginning of my vhdl project ?

Thanks in advance.

Matteo

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The FFT Megacore is a licensed core that is now freely available with the full version of Quartus (They use to charge $5000 for it).

    You use the megawizard to generate the core you need (FFT points, etc)

    Then you place it in your design either in VHDL or Verilog.

    It now works well, and uses the FPGA resources better than a similar core I wrote in verilog.

    I think you can still generate the core with the Web-pack, and use it, but it will time-out after 30 minutes or so, but I'm not positive. It should be available under DSP->Transforms in the megawizard, and in the wizard there's some links to documentation on it.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    anakha thank you very much for your hint! I find this solution very interesting. How can i place it in my VHDL project ?

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I'm a Verilog guy, not VHDL, so the terminology may be slightly different, but you should get the point.

    Once you generate the core it will have a verilog or vhdl top level module file that you include like any other sub-module in your design.

    There is also a .qip file that you include in your synthesis project. that will pull in all the various sub-modules in the design.

    For Simulation, in verilog they generatre a simulation only obfuscated file that you use in simulation with a <FFTmodulename>.vo extension. So I'm assuming they do something similar for VHDL. (They also have a matlab model that they provide if you prefer that method)

    Getting data into and out of the FFT core, uses some control signals *_sop, *_eop, etc. You'll need to read the documentation to get the signaling correct. If you are off on your control signals, your results will be invalid. The provide an "Error" output as well (I can't remember the exact name off the top of my head) but that will tell you if you've done something wrong on the control signaling.

    Once you start getting results out, they will be in a block floating point form, so if you are calculating magnitude you'll need to use the exponent bus to compare one set of results with the next.

    The documentation with the core is ok, but it is a bit tricky to get working correctly. Looking at the Error output in simulation will help you know you have it correct.

    Pete