No.
The problem is how to pass inputs and get the outputs using the Altera FPGA board. There is no relation with the PC at all.
There are the data:
assign inputdata [1] = 15;
assign inputdata [2] = 1;
assign inputdata [3] = 5;
assign inputdata [4] = 10;
assign inputdata [5] = 5;
assign inputdata [6] = 1;
assign inputdata [7] = 6;
assign inputdata [8] = 7;
assign inputdata [9] = 5;
assign inputdata [10] = 11;
assign inputdata [11] = 5;
assign inputdata [12] = 10;
assign inputdata [13] = 5;
assign inputdata [14] = 1;
assign inputdata [15] = 10;
assign inputdata [16] = 5;
assign inputdata [17] = 6;
assign inputdata [18] = 2;
assign inputdata [19] = 3;
assign inputdata [20] = 8;
assign inputdata [21] = 9;
assign inputdata [22] = 1;
assign inputdata [23] = 5;
assign inputdata [24] = 10;
assign inputdata [25] = 5;
assign inputdata [26] = 1;
assign inputdata [27] = 9;
assign inputdata [28] = 8;
assign inputdata [29] = 2;
assign inputdata [30] = 6;
assign inputdata [31] = 5;
assign inputdata [32] = 10;
assign inputdata [33] = 5;
assign inputdata [34] = 8;
assign inputdata [35] = 4;
assign inputdata [36] = 9;
assign inputdata [37] = 2;
assign inputdata [38] = 4;
assign inputdata [39] = 5;
assign inputdata [40] = 9;
assign inputdata [41] = 7;
assign inputdata [42] = 9;
assign inputdata [43] = 5;
assign inputdata [44] = 10;
assign inputdata [45] = 5;
assign inputdata [46] = 1;
assign inputdata [47] = 15;
assign inputdata [48] = 20;
assign inputdata [49] = 5;
assign inputdata [50] = 25;
assign inputdata [51] = 23;
assign inputdata [52] = 10;
assign inputdata [53] = 5;
assign inputdata [54] = 15;
assign inputdata [55] = 15;
assign inputdata [56] = 11;
assign inputdata [57] = 1;
assign inputdata [58] = 7;
assign inputdata [59] = 17;
assign inputdata [60] = 19;
assign inputdata [61] = 5;
assign inputdata [62] = 1;
assign inputdata [63] = 5;
assign inputdata [64] = 10;
These data are passed to the generated file but there is no output from the FFT generated file.