FFT Frequency Range

You haven't explained how is that you are using 50MHz clock to sample few KHz signal. Is it that your chirp is analogue and an ADC device is sampling at 50MHz ? or is your data digital in which case you cannot sample at such speed ?

Kaz, the chirp is analog and I am sampling via the ADC at 50MHz. Does that mean I need to decrease the sampling rate in order to narrow the range of the FFT?

Unfortunately yes. You are in a situation when you have upsampled the signal

Thanks for the quick reply! I'll try sampling around 200kHz and see if that does the trick. By the way, if I want to look at the FFT results in SignalTap, how do I change the SignalTap clock to match the clock of the ADC and FFT? I can't seem to apply my PLL block to SignalTap since it doesn't appear as a choice in the Signal Compiler block under the SignalTap II tab. Since the slowest internal clock of the FPGA is 50MHz (which would be my base clock), how do you suggest I apply a slower clock to SignalTap?

does that imply you will generate your ADC/fft clock from a PLL. I am not sure if PLL will support this low output. Whatever clock feeds fft/ADC you should be able to tap it to signaltap clock. Or you may add another copy of your clock and use it in signaltap.

Thanks again, kaz! I will mess around a bit more with clocks and PLLs, and hopefully I'll get it working soon.

Before you make changes you should know that with fft of 8192 resolution at speed of 50M you get each bin covering 6.104Khz i.e. about 8 bins will cover your signal (30~80KHz) on either side of dc. May be this enough

Actually I would like several hundred bins. The signal compiler tells me that the slowest clock I can obtain with the PLL is 5MHz. Maybe I'll be able to get away with that.

Do you have any suggestions for obtaining a 500kHz clock since the PLL won't work?

Normally ADCs require clean clock signal for sampling but since you are dealing with KHz you may try generate clock from fpga logic (divide using counter) and apply it to both ADC and FFT. It will have jitter but your application may tolerate it.