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RVanD5's avatar
RVanD5
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7 years ago

FFT Core - Variable streaming floating point - Arria 10. Output SOP and EOP are not aligned.

We are having trouble with the migration of the fixed point FFT core to the floating point FFT core on Arria 10. On example of strange behavior is seen in the the SignalTap below: the SOP en EOP markers are not aligned with the (de)assertion of the valid. We have not seen this before.

We have already clocked the core down from 300Mhz to a comfortable 200Mhz, but no change. We have not been able to reproduce this behavior in simulation.

Any suggestions?

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  • RVanD5's avatar
    RVanD5
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    7 years ago

    Hi,

    Enhancement?? Defect better describes it. IMHO it should be fixed in 17.1.

    The 16.1 core seems to be less optimized and runs on a lower maximum clock after fitting.

    We would like to run at 300MHz (same as the memory clock) which is on the edge of the 16.1 core in our design (probably some optimizations in the Arria 10 DSP IP).

    We will reimplement the affected IP.

    Regards, Rob