Honored Contributor
Honored ContributorHi,
Sorry to keep you waiting LarsD. I am still investigating on unity gain. The input to the IFFT block initially starts with FSM that generates 64 symbols (N = 64), 4 bits each symbol. Because IFFT block requires 8 bits, real and imaginary data, I use another block to mapped it to fit the requirement. The mapping it such as shown below: 0000 ---> -96 - j96 0001 ---> -96 - j32 0010 ---> -96 + j96 0011 ---> -96 + j32 0100 ---> -32 - j96 0101 ---> -32 - j32 0110 ---> -32 + j96 0111 ---> -32 + j32 1000 ---> 96 - j96 1001 ---> 96 - j32 1010 ---> 96 + j96 1011 ---> 96 + j32 1100 ---> 32 - j96 1101 ---> 32 - j32 1110 ---> 32 + j96 1111 ---> 32 + j32 Negative numbers represented in second compliment. Then the output from IFFT is connected directly to FFT. After that, in order to do scaling, I created another block for that by refering to the source given by 'thepancake', did some modification and wrote the code in VHDL. So I test the blocks with single type of symbols first, meaning all the 64 symbols are 0000 or 0001 or 0010 and so on until 1111. I find that the final output that I get is the same with the input to the IFFT block. However, when I tried mixing several symbols together in the 64-length, then the results becomes different, it is not the same as the my input to the IFFT block. I attached my project files, in that project the 64-length input is 1111,1111,1111,1111,0000,1111,...,1111 (total 64 symbols). The output is completely different from what I expected. Suppose the output should be 32 + j32, 32 + j32, 32 + j32, 32 + j32, -96 - j96, 32 + j32, ... ,32 + j32. But the output turns out to be 32 + j32, 32 + j32, 32 + j32, 32 + j32, -144 - j144, 32 + j32,..., 48 + j48, 32 + j32, ..., 64 + j64,32 + j32,... ,32 + j32. Need to run the project to see total waveform. I used functional simulation mode. The device is Cyclone II. Quartus 8.1 web edition. I wonder what caused the output to be like that.:confused:
