false-start recovery for UART core

Hello Everyone!

I have a system with cyclone V FPGA running NIOS II.

The FPGA controls power up/down (using relay) of a computing node that is also connected to NIOS processor using UART core.

We have a situation that when the FPGA turns-off the computing node , the uart core stops working (and also all other uart cores in the same design ) . We have concluded that this is due to a situation called "false-start" on uart , meaning that because after power up , the UART signal goes low , the core intercept the High to Low transition to a start bit without data afterwards.

looking at the documentations : https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf

it is noted (on chapter 8) that the core supports "False-start detection " but as said we see that this condition stucks the system.

so the question is whether the code needs to implement something to allow proper operation of "False start detection" feature like reading a status register?

appreciate your help :)

Pini.S