false_path issue seen in the STA tool when running 'check_timing'

Hi @Knug

Sorry for the late response.

In Check Timing, the no_input_delay check verifies that every input port that is not determined to be a clock has an input delay assignment. Thus the message reported.

Reference: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#analyze/sta/sta_com_check_timing.htm

You might have wrote a wrong sdc command thus no unconstrained paths reported.

In the Timing Analyzer, you can set false path by clicking Constraints > Set False Path to ensure that the tool recognize the paths.

You may checkout the user guide here on set_false_path sdc command and its example.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-scripting.pdf

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.