Knug
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How to properly constrain bidirectional I2C SCL / SDA ports ?
Hi, We are using an I2C slave controller and like to know how to properly constrain bidirectional SDA and SCL lines to meet setup and hold time requirements. I searched on the internet and cannot find anywhere advising what constraints to use for I2C SDA, SCL bidirectional ports. Will they be also different constraints for eg START, STOP conditions etc? I will appreciate if you can advise with an example of SDC constraints. Our I2C interface within the I2C controller module follows the defined behaviour of a I2C slave in the NXP specification (https://www.nxp.com/docs/en/user-guide/UM10204.pdf) We are using stability check components (checkstable digital filters for the read sda/scl condition to ensure only stable values of SDA and SCL are used by testing over a period of 10 clock cycles (100nS per cycle) that the bit has not changed) for SDA and SCL set to the shortest setting to ensure this works with the 10MHz clock that is used for our FPGA Cyclone V. We are using a higher frequency clock (10MHz) driving state machine i2c_fsm, bus_strobe process etc. The transfer can occur over speed of 100kbits/s in standard mode. Your prompt reply to this matter will be appreciated. Regards, Kevin1.5KViews0likes1CommentRe: Trying to constrain I2C interface
I have the same query. How to properly constrain bidirectional I2C SCL/SDA lines ? Added this at the moment BUT I also have to generate the Output SCL clock #I2C 100KHz clock (standard mode) create_clock -name {fpga_i2c_scl_clk} -period 10000.000 -waveform { 0.000 5000.000 } [get_ports {FPGA_I2C_SCL}] Need to constrain SDA wrt different conditions listed above too. Please advise Any updates on this will be appreciated.4.1KViews0likes0CommentsRe: How to properly constrain the PFL for STA
Hi @JohnT_Intel My last 3 Messages to the private email got back : Delivery has failed to these recipients or groups: noreply@community-mail.intel.com (noreply@community-mail.intel.com) <mailto:noreply@community-mail.intel.com> Your message couldn't be delivered. Despite repeated attempts to deliver your message, querying the Domain Name System (DNS) for the recipient's domain location information failed.401Views0likes0CommentsRe: How to properly constrain the PFL ? Differences between 2 docs. Which one is right?
Wrt : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf fpga_dclk constraint for input clock to DCLK ratio = 1 (see page 29) create_generated_clock - source pfl_clk -invert <fpga_dclk_port> I have used same constraint as above BUT have the following question : Q/ Is there a special reason to why -invert is suggested here ? Like a reply to this please.1.4KViews0likes0CommentsRe: How to properly constrain the PFL ? Differences between 2 docs. Which one is right?
No reply here to this. I also sent same message to the following private email BUT got back : Delivery has failed to these recipients or groups: noreply@community-mail.intel.com (noreply@community-mail.intel.com) Your message couldn't be delivered. Despite repeated attempts to deliver your message, querying the Domain Name System (DNS) for the recipient's domain location information failed.1.4KViews0likes0CommentsRe: How to properly constrain the PFL ? Differences between 2 docs. Which one is right?
Or I think : Bidirectional synchronous: flash_data Read mode (Flash ROM to PFL) should be listed here on page 28 and NOT PFL to Flash ROM set_max_delay -from <port> -to pfl_clk IS THEN CORRECT Write Mode should then state (PFL to Flash ROM) and NOT Flash ROM to PFL Is this correct?1.5KViews0likes1CommentRe: How to properly constrain the PFL ? Differences between 2 docs. Which one is right?
Both documents state now : eg https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf on page 28 : Bidirectional synchronous: flash_data Read mode (PFL to Flash ROM) is listed here on page 28. set_max_delay -from <port> -to pfl_clk Is this right ? PFL to Flash ROM direction looks to be output from the PFL (ie flash_data is out for READ mode. Isn’t this the case?) so the set_max_delay constraint suggested above should be : set_max_delay -from pfl_clk -to <port> Isn’t this the case here ?1.5KViews0likes2CommentsRe: Can I set a weak pull up resistor on an output port ?
I did not finally set a weak pull up resistor on fpga_nconfig.It had already a 10k pull-up. I resolved the issue I had by myself to why FPGA was NOT configured after successful flash programming Wrt other tickets raised had to delay the pfl_nreset to get the 1 PFL solution to work.995Views0likes0Comments