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Honored Contributor
Honored Contributorfail to access DDR2 SDRAM with Stratix III EP3SL340F1517I3
We are trying to implement a DDR2 controller example in an FPGA board designed by ourselves. The function simulation with the DDR2 controller IP is good in the modelsim. But after generating it in th...
Altera_ForumHonored Contributor
Honored ContributorCould you have some unused pins connected to ground on the board, that have been set as outputs driving high in Quartus? (or the other way round)
