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EdCz's avatar
EdCz
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29 days ago

F-Tile xcvr placement on DK-DEV-AGF023FA

I have an  Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF023F.  I have 1 F-Tile working with PCIe Gen4x16, and want to use the second for 400Gb Ethernet. I have used the F-Tile channel p...
Ethernet
Transceiver
EdCz's avatar
EdCz
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20 days ago

The multiple clock error is deep inside of a hierarchy generated by Quartus.  I have tried many configurations of the F-Tile and its clocking IP, but without success.  

As for the 400G example design, while I can generate an example design, Quartus does not support the F-Series Development Kit 2xF-Tile DK-DEV-AGF023F. as a target device.  Since I can successfully compile for other devices, I am assuming my configurations are correct.

This is blocking our use of the dual- F-Tile device for ethernet.  Are you able to generate a 400G Ethernet for the 2xF-Tile dev kit?

Thanks, Ed.

RongY_altera's avatar
RongY_altera
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20 days ago

You're right. The generated example design is not directly for your target dev kit thus your problem is likely something wrong when you do the design migration.

 

For the DK-DEV-AGF023FA, your design should use Bank12C, FGTL12C_RX/TX_Q2/Q3 for the 400G, REFCLK_FGTL12C_Q3_RX_CH6P/N for the clock. Based on these pins, your 400G example design still has compilation error. Is my understanding correct?

 

Regards,

Rong