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Matt_P's avatar
Matt_P
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2 years ago

F-Tile Reference and System PLL Clocks IP

Hello FPGA Forum, I'm working with the IP "F-Tile Reference and System PLL Clocks Intel FPGA" IP and the 'Multi Channel DMA for PCI Express' example design. I'm trying to understand the connection...
Pcie
VenT_Altera's avatar
VenT_Altera
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2 years ago

Hi @Matt_P,


Thanks for your reply.


For the Refclk source of System PLL in the F-tile Reference and System PLL Clocks IP, the naming of RefClk # is fixed. The user can choose one of the 8 RefClk from RefClk[0] to RefClk[7] as the Refclk source for the System PLL.


You may enable the desired Refclk # for FGT PMA from Refclk#0 to Refclk #9. If you want the Refclk #2 instead of Refclk#3, you may enable the Refclk#2.


Thanks.

Best Regards,

VenTing_Intel


yanghao1's avatar
yanghao1
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2 years ago

Hi @ventt ,

I have another question about this PLL IP.

In the pinout, FGT REFCLK PIN is differential clock input, (also dont care the 8 and 9), but PLL input port is single-ended. How can I connect the differential clock input pin to the PLL ip?