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Matt_P's avatar
Matt_P
Icon for New Contributor rankNew Contributor
2 years ago

F-Tile Reference and System PLL Clocks IP

Hello FPGA Forum, I'm working with the IP "F-Tile Reference and System PLL Clocks Intel FPGA" IP and the 'Multi Channel DMA for PCI Express' example design. I'm trying to understand the connection...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @Matt_P,


Thanks for reaching out to the Intel Community Forum.


You may refer to the user guide below to learn more about the implementing of the F-Tile Reference and System PLL Clocks Intel® FPGA IP:

https://www.intel.com/content/www/us/en/docs/programmable/683872/23-4-4-7-0/implementing-the-76863.html


You may check out the refclk of MCDMA IP for PCIe in the Section 4.2 Clocks of the user guide below:

https://www.intel.com/content/www/us/en/docs/programmable/683821/23-3/clocks.html


Thanks.

Best Regards,

VenTing_Intel