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UserID4331231
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4 days ago

F-Tile Ethernet Hard IP Design Example - Testbench

I have a question regarding this Ftile Ethernet hard IP example Design.  I am able to generate this example design for 400gbe. I am able to load this design (sof) to  MA2700Kit. I was able to run tcl script and internal loopback test was successful. I was also able to run testbench basic_avl_tb_top.sv and VSIM run was successful.

I have following questions and areas where I need help.

  • At line 144 and 145 in basic_avl_tb_top.sv I can see that Tx outputs are assigned Rx input pins. I would like to understand reason for doing this? I mean shouldn’t the RX lines driven by tasks/function to simulate incoming packets over the ethernet link?
  • I want to modify the testbench to simulate Receiving of a particular 98 byte ethernet frame, and check how mac segmented interface is behaving to communicate this frame; So i can write my custom RTL block to receive it properly.
  • I need help developing tasks/function to simulate incoming packets over the ethernet link.

Thank you

1 Reply

  • Hello Ankit,

     

    This direct assignment is a common testbench practice to verify that the design's transmit (Tx) path can loop back and be received (Rx) correctly within the same simulation. It creates a closed loop, allowing you to check the integrity of the internal data path and functional correctness without external stimulus.
    This setup doesn't simulate real incoming Ethernet traffic from an external device. For true packet injection and more realistic testing, Rx signals should be driven by tasks or functions that model external traffic.

     

    You may probably remove/comment out the Tx-to-Rx loopback in basic_avl_tb_top.sv and write a verilog function to send your 98-byte Ethernet frame on the Rx interface. 

     

    Regards,

    Pavee