F-Tile Ethernet Hard IP Design Example - Testbench

Hello Ankit,

This direct assignment is a common testbench practice to verify that the design's transmit (Tx) path can loop back and be received (Rx) correctly within the same simulation. It creates a closed loop, allowing you to check the integrity of the internal data path and functional correctness without external stimulus.
This setup doesn't simulate real incoming Ethernet traffic from an external device. For true packet injection and more realistic testing, Rx signals should be driven by tasks or functions that model external traffic.

You may probably remove/comment out the Tx-to-Rx loopback in basic_avl_tb_top.sv and write a verilog function to send your 98-byte Ethernet frame on the Rx interface. 

Regards,

Pavee