RHobb
Occasional Contributor
Occasional ContributorExternal Memory Interface IP on Stratix 10
I have a design incorporating the EMIF IP for a Stratix 10 chip (Terasic Apollo S10 dev kit). I generated the design example and simulated it using the Avalon Verification IP Suite and BFM. I’ve read...
I solved the problem:
the waitrequest signal is active low. I was triggering my logic on active high.
this isn’t immediately relevant from reading the Avalon spec but mere oversight by not seeing the signal in the IP block diagram.
