Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Exporting DSP Builder Modules to HDL Designs

Hi We're considering purchasing the Quartus toolset for an upcoming project, in which we need to take logic created with DSP Builder and integrate it into a behavioral VHDL design, which would...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

try opening SignalCompiler and going to the Export tab, click Export, and select an output directory.

open the .qip to see what VHDL files are involved in the design and create your ModelSim script based on them. it may be a little trickier if you're using any MegaFunctions, you'll have to gather the .vho simulation model and any .hex/.mif used by the core.