example avalon slave code in VHDL

Do you know a little bit about SOPC Builder?

You could start a clean Quartus II project, open the SOPC Builder, Create New System by choosing VHDL as Target HDL. Then add:

1) a Nios proc (just default) for having an avalon master (otherwise there will be an error message)

2) an Onchip Ram (System Contents -> Altera SOPC Builder -> Avalon Components -> Memory-> On-Chip Memory) with e.g. 1kBytes (default for exception and reset address, otherwise there will be an error message)

3) an Interval Timer (System Contents -> Altera SOPC Builder -> Avalon Components -> Others -> Interval Timer).

Then go to the tap 'System Generation' and click 'Generate'.

After generating that SOPC Builder project you will find a timer_0.vhd in you Quartus II project folder. This is quite simple VHDL code with an Avalon Slave Interface. You can try out some parameter settings of the Interval Timer and compare the results in the VHDL file. Keep in mind, that it's really just an example, depending on your needs, the avalon memory mapped slave interface signals can differ. For example, maybe you will never need an interrupt signal. For further information refer to the manual for the avalon memory mapped interface.

Thanks Herbert,

That helped!

I mannaged to create components with all the interfaces I need.

I worked earlier with Xilinx tools. But these Altera tools are very good!

I also required the same slave templates in VHDL. your replies got helpful.

thanks to everyone.