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ZaidSahawneh's avatar
ZaidSahawneh
Icon for New Contributor rankNew Contributor
2 years ago

Ethernet fails to establish on boot

I have a rather complicated design on a Stratix 10 FPGA. We control our design through SSH over an ethernet connection.

Recently, I added Intel's Stratix 10 Temperature Sensor IP.

It seems that when the temperature sensor is instantiated, if I have too many instances enabled in my Signal Tap STP file, the ethernet link fails to come up. But if I comment out the temperature sensor's instantiation, I can re-enable all of my signal tap instances without any issue. I've only gotten ethernet with the temperature sensor if I have only 1-2 signal tap instances enabled.

I've only done a small set of sample compilations and there isn't any additional pattern to the problem at this stage. What sort of behavior could be causing the ethernet link to not establish on boot like normal? What kinds of tests should I run to help diagnose the underlying issue?

I'm being pointed towards the ethernet reset signal as the cause. Perhaps it isn't being held for long enough but I'm unsure about the best way to either test this or patch if it is the root cause.

Any help/direction is appreciated. Thank you.

Ethernet

2 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    Diagnostic

    1. Ensure the design meets timing requirements, especially in paths related to the Ethernet and reset signals.
    2. Test the Ethernet functionality with the temperature sensor IP alone, and then add Signal Tap instances incrementally to identify the point of failure.
    3. Use Signal Tap to monitor the Ethernet PHY reset signal duration during boot. Compare this duration against the PHY's datasheet requirements.
    4. Monitor the power supply voltages during boot using an oscilloscope to detect any noise or voltage drops.

    Steps to Verify and Adjust Ethernet Reset Signal

    1. Use Signal Tap to capture the reset signal and verify its duration during boot.

    2. Modify the reset generation logic in your design to increase the reset signal duration. This might involve adding a counter to hold the reset signal active for a longer period.

    3. Test with different reset durations to determine if a specific duration resolves the issue.

    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

    Best regards,

    zying