Error when simulating generated RAM IPcore in ModelSim

Hi all,

I am trying to simulate a 1-port RAM that I created using Quartus 17.1.

I wrote a test bench, ram_tb.v, and included the instantiation files "intel_1portBRAM" & "intel_1portBRAM_ram_1port_171_4x26sya" to ModelSim.

I managed to compile the files, however, when I try to start simulation, I get the following error message.

"Instantiation of 'altera_syncram' failed. The design unit was not found."

What do I need to do in order to resolve this error.

Your assistance on this matter is greatly appreciated!

Thanks!