Error (10773): Verilog HDL error SystemVerilog extensions

Well, there's a problem.

Error (10773): Verilog HDL error at timer_control.v(5): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions

This warning came up, so I did System Verilog extensions when I set up the module... Probably.
But this error still pops up. Is there a solution?

<code>

module timer_control(RESET, CLK, SW, DATA);

input RESET, CLK;
input [2:0] SW;
output [7:0] DATA [31:0]; //<-- This is an error code!

integer count;

reg [6:0] min, sec, m_sec;
reg [6:0] rec_min, rec_sec, rec_m_sec;

reg start, lab;

always @ (posedge CLK) begin
if(~RESET) begin
count = 0;
end
else if(start) begin
if(count == 10) begin
count = 0;
m_sec = m_sec + 1;
end
else begin
count = count + 1;
end
if(m_sec == 100) begin
m_sec = 0;
sec = sec + 1;
end
if(sec == 60) begin
sec = 0;
min = min + 1;
end
if(min == 60) begin
min = 0;
end
end

end

always @ (*) begin
if(~RESET) begin
start = 0;
rec_min = 0;
rec_sec = 0;
rec_m_sec = 0;
lab = 0;
end

if(SW[2])
start = 1;

if(SW[1])
start = 0;

if(SW[0]) begin
rec_min = min;
rec_sec = sec;
rec_m_sec = m_sec;
lab = 1;
end
end

binary_to_digit min_control (min, MIN_FRONT, MIN_END);
binary_to_digit sec_control (sec, SEC_FRONT, SEC_END);
binary_to_digit s_sec_control(m_sec, HOUR_FRONT, HOUR_END);

endmodule