Error (10773): Verilog HDL error SystemVerilog extensions

You're putting a 2D array on an output instead of an internal RAM (which is what I'm guessing you are trying to implement). Shouldn't this be not in the port list like this:

reg [7:0] DATA [31:0];

Found a super old post that might help as well:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/SystemVerilog-Extensions-Error/m-p/171487#M42427%3Fwapkw=quartus%20error%2010773