Forum Discussion
assn1
New Contributor
New ContributorError (10773): Verilog HDL error SystemVerilog extensions
Well, there's a problem.
Error (10773): Verilog HDL error at timer_control.v(5): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions
This w...
sstrell
Super Contributor
Super ContributorYou're putting a 2D array on an output instead of an internal RAM (which is what I'm guessing you are trying to implement). Shouldn't this be not in the port list like this:
reg [7:0] DATA [31:0];
Found a super old post that might help as well:
