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assn1's avatar
assn1
Icon for New Contributor rankNew Contributor
3 years ago

Error (10773): Verilog HDL error SystemVerilog extensions

Well, there's a problem. Error (10773): Verilog HDL error at timer_control.v(5): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions This w...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
3 years ago

(1) The output port DATA is never referenced in your module code. So is it really needed?

(2) You can't use multidimensional arrays in ports in verilog. Use DATA[255:0] instead and manually assign bit fields.

(3) Use the <CODE> block feature of this forum. It makes your code MUCH easier to read and understand.