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Altera_Forum
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11 years ago

Endianess of Avalon-ST Packets to PCI Express TLPs for IP Compiler for PCI Express

Hi, we are using PCIE Express Hard IP to interface both PowerPC and Intel X86. The difference that influences our FPGA user logic is the endianness of two processors. PowerPC is Big ...
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Altera_Forum
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11 years ago

"It seems headers are little endian, payloads are big endian."

I think your understanding for "Notes to Figure 5–17' is the opposite:

Supposingly it should be headers are big endian, whereas data payloads are little endian format.

Data_byte0 would be the first byte sent after the header and is associated with the lowest (start) address