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Altera_Forum
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11 years ago

Endianess of Avalon-ST Packets to PCI Express TLPs for IP Compiler for PCI Express

Hi, we are using PCIE Express Hard IP to interface both PowerPC and Intel X86. The difference that influences our FPGA user logic is the endianness of two processors. PowerPC is Big ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

There is no option to set the endianness in Megawizard.