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Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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EMIF Cyclone 10 GX: emif_usr_clk frequency incorrect

Hi, i've instantiated the EMIF IP core to connect to a DDR3 SODIMM memory on a customer board. The EMIF is fed by a configurable clock generator. Some information: - pll_ref_clk frequency: 100MH...
  • yoichiK_altera's avatar
    yoichiK_altera
    5 years ago

    In the top.sdc you are setting pll reference clock as 50Mhz and this causes the incorrect emif_usr_clk frequency. Please remove the following constraint from sdc then you should see the correct clock frequency in the report. The pll reference clock frequency is defined in the IP sdc.

    create_clock -name {clk_emif} -period 20.0 [get_ports {emif_clk_clk}]

yoichiK_altera's avatar
yoichiK_altera
Icon for Contributor rankContributor
5 years ago

Hi

If your memory clock is 800Mhz and quarter rate for user logic is chosen emif_usr_clk frequency should be 200Mhz.

Can you attach your QAR design in this forum ?

  • yoichiK_altera's avatar
    yoichiK_altera
    Icon for Contributor rankContributor
    5 years ago

    Hi

    When I compile the design I see the emif_usr_clk is reported as 200Mhz in the clocks GUI. Can you confirm ?

    • Schroeti's avatar
      Schroeti
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Yes, exactly as I logged. Sorry, I forgot to change the reference clock back away from 50MHz before generating the qar.

      Would you please set the emif pll reference clock to 200MHz, then you should see the effect.

      • yoichiK_altera's avatar
        yoichiK_altera
        Icon for Contributor rankContributor
        5 years ago

        In the top.sdc you are setting pll reference clock as 50Mhz and this causes the incorrect emif_usr_clk frequency. Please remove the following constraint from sdc then you should see the correct clock frequency in the report. The pll reference clock frequency is defined in the IP sdc.

        create_clock -name {clk_emif} -period 20.0 [get_ports {emif_clk_clk}]